Binary-Coded Ternary: Difference between revisions
Created page with "<b>Binary-coded Ternary (BCT)</b> is an implementation of ternary logic built on top of normal binary logic. Using two bits or wires per trit as the base. Sub-circuits made with binary logic gates can emulate the truth tables of ternary logic gates. This implementation is useful with logic simulators and would most likely function on an FPGA. However because each trit needs two wires a design would be extremely bloated with interconnects and bus lines. Doubling the wiri..." |
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<b>Binary-coded Ternary (BCT)</b> is an implementation of ternary logic built on top of normal binary logic. Using two bits or wires per trit as the | <b>Binary-coded Ternary (BCT)</b> is an implementation of ternary logic built on top of normal binary logic. Using two bits or wires per trit as the foundation. Sub-circuits made with normal binary logic gates can emulate the truth tables of ternary logic gates. The rest of a ternary computer can be made out of these BCT sub-circuits. | ||
This implementation is useful with logic simulators and would most likely function on an FPGA. | This implementation is useful with existing binary logic simulators and would most likely function on an FPGA. | ||
Because each trit uses two wires any design based on BCT is going to be more complex in its routing as there will be double the bus wires. This would take up more space in an IC design and would increase costs in a PCB design. More advanced multilayer designs can likely deal with the extra wires with minimal penalties. It is likely the two wires could be treated just like differential pairs, e.g., PCIe high speed differential pairs. | |||
BCT can be built out of CMOS for speed and power efficiency. Native three state logic with transistors is slow and power hungry as the zero state is a small short; effectively a voltage divider. | |||
<div style="text-align: center;"> | <div style="text-align: center;"> | ||
Latest revision as of 10:27, 17 July 2025
Binary-coded Ternary (BCT) is an implementation of ternary logic built on top of normal binary logic. Using two bits or wires per trit as the foundation. Sub-circuits made with normal binary logic gates can emulate the truth tables of ternary logic gates. The rest of a ternary computer can be made out of these BCT sub-circuits.
This implementation is useful with existing binary logic simulators and would most likely function on an FPGA.
Because each trit uses two wires any design based on BCT is going to be more complex in its routing as there will be double the bus wires. This would take up more space in an IC design and would increase costs in a PCB design. More advanced multilayer designs can likely deal with the extra wires with minimal penalties. It is likely the two wires could be treated just like differential pairs, e.g., PCIe high speed differential pairs.
BCT can be built out of CMOS for speed and power efficiency. Native three state logic with transistors is slow and power hungry as the zero state is a small short; effectively a voltage divider.
| BCT | ||
| N | P | T |
| 0 | 0 | 0 |
| 0 | 1 | + |
| 1 | 0 | - |
| 1 | 1 | ? |
