Binary-Coded Ternary: Difference between revisions
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<b>Binary-coded Ternary (BCT)</b> is an implementation of ternary logic built on top of normal binary logic. Using two bits or wires per trit as the base. Sub-circuits made with binary logic gates can emulate the truth tables of ternary logic gates. | |||
<p>This implementation is useful with existing binary logic simulators and would most likely function on an FPGA. However because each trit needs two wires a design would be extremely bloated with interconnects and bus lines. Doubling the wiring and logic and loosing most of the advantages of a ternary computer.</p> | <p>This implementation is useful with existing binary logic simulators and would most likely function on an FPGA. However because each trit needs two wires a design would be extremely bloated with interconnects and bus lines. Doubling the wiring and logic and loosing most of the advantages of a ternary computer.</p> | ||
<p>BCT can be built out of CMOS for speed and power efficiency. Native three state logic with transistors is slow and power hungry as the zero state is a small short.</p> | |||
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Latest revision as of 11:00, 22 April 2025
Binary-coded Ternary (BCT) is an implementation of ternary logic built on top of normal binary logic. Using two bits or wires per trit as the base. Sub-circuits made with binary logic gates can emulate the truth tables of ternary logic gates.
This implementation is useful with existing binary logic simulators and would most likely function on an FPGA. However because each trit needs two wires a design would be extremely bloated with interconnects and bus lines. Doubling the wiring and logic and loosing most of the advantages of a ternary computer.
BCT can be built out of CMOS for speed and power efficiency. Native three state logic with transistors is slow and power hungry as the zero state is a small short.
| BCT | ||
| N | P | T |
| 0 | 0 | 0 |
| 0 | 1 | + |
| 1 | 0 | - |
| 1 | 1 | ? |
