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Created page with "== Circuitverse == * Optimizing Multiplier to Speed Up Result Output ** Parallelizing Adds (A+B)+(C+D)+(E+F) ** Multiplier Specific Carry Select Adder ** Karatsuba Algorithm? == Hung Up On == * Opcodes Operands Addressing Modes ** Choosing Registers ** Choosing Instructions *** Ordering Instructions ** Choosing Addressing Modes == Exploring Ideas == * Expanding from 6-trit to 9-trit. ** Instruction decoding would be easier. 6 trits for opcode and 3 trits for addressing..." |
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Revision as of 13:00, 13 April 2025
Circuitverse
- Optimizing Multiplier to Speed Up Result Output
- Parallelizing Adds (A+B)+(C+D)+(E+F)
- Multiplier Specific Carry Select Adder
- Karatsuba Algorithm?
Hung Up On
- Opcodes Operands Addressing Modes
- Choosing Registers
- Choosing Instructions
- Ordering Instructions
- Choosing Addressing Modes
Exploring Ideas
- Expanding from 6-trit to 9-trit.
- Instruction decoding would be easier. 6 trits for opcode and 3 trits for addressing mode.
- Although 7 trits would be interesting. 5 trits for opcode and 2 trits for addressing mode.
- Odd length widths would solve a thing.
