FPGA: Difference between revisions
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Created page with "I do not have any hands-on experience with FPGAs yet and do not want to get into FPGAs until I have a stable T729 design already. I won't know what size FPGA to get until the T729 architecture is mostly complete. Large FPGAs can get quite expensive. I foresee some limitations running a ternary project on an FPGA. * FPGAs can only do binary. Must use ADC and DACs to handle analog signals. ** Only BCT implementation would work on an FPGA. * Memory..." |
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I do not have any hands-on experience with FPGAs yet and do not want to get into FPGAs until I have a stable | I do not have any hands-on experience with FPGAs yet and do not want to get into FPGAs until I have a stable TNINE design already. I won't know what size FPGA to get until the TNINE architecture is mostly complete. Large FPGAs can get quite expensive. | ||
I foresee some limitations running a ternary project on an FPGA. | I foresee some limitations running a ternary project on an FPGA. | ||
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** Only [[Binary-Coded Ternary|BCT]] implementation would work on an FPGA. | ** Only [[Binary-Coded Ternary|BCT]] implementation would work on an FPGA. | ||
* Memory access. | * Memory access. | ||
** Ternary decoder to binary encoder would allow for sequential access of binary SRAM/DRAM. However, would consume a lot of logic and be | ** Ternary decoder to binary encoder would allow for sequential access of binary SRAM/DRAM. However, would consume a lot of logic and be slow. | ||
** Direct mapping; | ** Direct mapping; 18-trit BCT fits in 29-bits, but that's not a normal size so 32-bits. Wiring the 18-trit BCT memory address space directly to 32-bit address 16-bit wide memory will be fast but a massive amount of the memory would never be accessed. | ||
*** ( | *** | ||
=== Numbers === | |||
* 18-trit = (3<sup>18</sup>) 387420489 | |||
* 387420489 Trytes * 9 = 3486784401 trits | |||
* 3486784401 trits * 2 bits = 6973568802 bits | |||
* 6973568802 bits = ~871696101 Bytes | |||
* 871696101 Bytes = ~831.32MBs | |||
Latest revision as of 10:59, 17 July 2025
I do not have any hands-on experience with FPGAs yet and do not want to get into FPGAs until I have a stable TNINE design already. I won't know what size FPGA to get until the TNINE architecture is mostly complete. Large FPGAs can get quite expensive.
I foresee some limitations running a ternary project on an FPGA.
- FPGAs can only do binary. Must use ADC and DACs to handle analog signals.
- Only BCT implementation would work on an FPGA.
- Memory access.
- Ternary decoder to binary encoder would allow for sequential access of binary SRAM/DRAM. However, would consume a lot of logic and be slow.
- Direct mapping; 18-trit BCT fits in 29-bits, but that's not a normal size so 32-bits. Wiring the 18-trit BCT memory address space directly to 32-bit address 16-bit wide memory will be fast but a massive amount of the memory would never be accessed.
Numbers
- 18-trit = (318) 387420489
- 387420489 Trytes * 9 = 3486784401 trits
- 3486784401 trits * 2 bits = 6973568802 bits
- 6973568802 bits = ~871696101 Bytes
- 871696101 Bytes = ~831.32MBs
