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== Ternary Logic Gates == | == Ternary Logic Gates == | ||
<table style="margin: auto;"> | |||
<tr> | |||
<th>'''Balanced'''</th> | |||
<th>'''Unsigned'''</th> | |||
</tr> | |||
<tr> | |||
<td style="margin: 50%; width: 150px;"> | |||
* '''+2 Input''' | |||
** [[SUM (Ternary Gate)|SUM]] | |||
** [[CON (Ternary Gate)|CON]] | |||
** [[ANY (Ternary Gate)|ANY]] | |||
*** [[ | ** [[MUL (Ternary Gate)|MUL]] | ||
*** [[ | ** [[COM (Ternary Gate)|COM]] | ||
*** [[ | ** [[MIN (Ternary Gate)|MIN]] | ||
*** [[ | ** [[MAX (Ternary Gate)|MAX]] | ||
* '''1 Input''' | |||
** [[NEG (Ternary Gate)|NEG]] | |||
** [[RDN (Ternary Gate)|RDN]] | |||
** [[RUP (Ternary Gate)|RUP]] | |||
** [[NTB (Ternary Gate)|NTB]] | |||
** [[PTB (Ternary Gate)|PTB]] | |||
</td> | |||
<td style="margin: 50%; width: 150px; vertical-align: text-top;"> | |||
* '''+2 Input''' | |||
** [[USUM (Ternary Gate)|SUM]] | |||
** [[UCON (Ternary Gate)|CON]] | |||
** [[UCAD (Ternary Gate)|CAD]] | |||
</td> | |||
</tr> | |||
</table> | |||
</div> | </div> | ||
<div class="mainpage_box"> | <div class="mainpage_box"> | ||
== Binary Logic Gates == | == Binary Logic Gates == | ||
* '''+2 Input''' | * '''+2 Input''' | ||
| Line 119: | Line 135: | ||
* [[MUL (BCT)|MUL]] | * [[MUL (BCT)|MUL]] | ||
* [[SUM (BCT)|SUM]] | * [[SUM (BCT)|SUM]] | ||
* [[ | * [[RDN (BCT)|RDN]] | ||
* [[ | * [[RUP (BCT)|RUP]] | ||
</div> | </div> | ||
<div class="mainpage_box"> | <div class="mainpage_box"> | ||
=== Logic === | === Logic === | ||
* [[MUX (BCT)|MUX]] | * [[MUX (BCT)|MUX]] | ||
Latest revision as of 22:08, 5 March 2026
TNINE Balanced Ternary Computer
Hobby Project
Ternary Logic Gates
| Balanced | Unsigned |
|---|---|
Logic
Processor
Computer
Programming
Other Implementations
Binary-Coded Ternary Circuits
Logic
Operations
