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== Ternary Logic Gates == | == Ternary Logic Gates == | ||
<table> | <table style="margin: auto;"> | ||
<tr> | <tr> | ||
<th>'''Balanced'''</th> | <th>'''Balanced'''</th> | ||
<th>'''Unsigned'''</th> | <th>'''Unsigned'''</th> | ||
</tr> | </tr> | ||
<tr> | <tr> | ||
<td> | <td style="margin: 50%; width: 150px;"> | ||
* '''+2 Input''' | * '''+2 Input''' | ||
** [[SUM (Ternary Gate)|SUM]] | ** [[SUM (Ternary Gate)|SUM]] | ||
| Line 46: | Line 46: | ||
** [[NTB (Ternary Gate)|NTB]] | ** [[NTB (Ternary Gate)|NTB]] | ||
** [[PTB (Ternary Gate)|PTB]] | ** [[PTB (Ternary Gate)|PTB]] | ||
</td> | </td> | ||
<td style="vertical-align: text-top;"> | <td style="margin: 50%; width: 150px; vertical-align: text-top;"> | ||
* '''+2 Input''' | * '''+2 Input''' | ||
* [[USUM (Ternary Gate)|SUM]] | ** [[USUM (Ternary Gate)|SUM]] | ||
* [[UCON (Ternary Gate)|CON]] | ** [[UCON (Ternary Gate)|CON]] | ||
* [[ | ** [[CAD (Ternary Gate)|CAD]] | ||
</td> | </td> | ||
</tr> | </tr> | ||
</table> | </table> | ||
</div> | </div> | ||
Latest revision as of 00:22, 6 March 2026
TNINE Balanced Ternary Computer
Hobby Project
Ternary Logic Gates
| Balanced | Unsigned |
|---|---|
Logic
Processor
Computer
Programming
Other Implementations
Binary-Coded Ternary Circuits
Logic
Operations
