Index: Difference between revisions
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| Line 42: | Line 42: | ||
* '''1 Input''' | * '''1 Input''' | ||
** [[NEG (Ternary Gate)|NEG]] | ** [[NEG (Ternary Gate)|NEG]] | ||
** [[ | ** [[RDN (Ternary Gate)|RDN]] | ||
** [[ | ** [[RUP (Ternary Gate)|RUP]] | ||
** [[NTB (Ternary Gate)|NTB]] | ** [[NTB (Ternary Gate)|NTB]] | ||
** [[PTB (Ternary Gate)|PTB]] | ** [[PTB (Ternary Gate)|PTB]] | ||
Revision as of 11:16, 5 March 2026
TNINE Balanced Ternary Computer
Hobby Project
Ternary Logic Gates
| Balanced | Unsigned |
|---|---|
Logic
Processor
Computer
Programming
Other Implementations
Binary-Coded Ternary Circuits
Logic
Operations
