Index

TNINE Balanced Ternary Computer

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Wiki

• About
• Project Goals
• Current Focus
• Ternary vs Binary
• AI Notice
• Quantum

Groups

Discord

• Ternary Computing Community

Ternary Logic Gates

Balanced	Unsigned
+2 Input SUM CON ANY MUL COM MIN MAX 1 Input NEG RDN RUP NTB PTB	+2 Input SUM CON CAD

Binary Logic Gates

• +2 Input
  • XOR
  • AND
  • OR

• 1 Input
  • NOT

Logic

• Full Adder

Ternary Compute

• Shift
• Rotate
• Add
• Multiply

Processor

• Registers
• ALU
• Instructions
• Instruction Set Map
• Memory
• IO

Computer

• Terminal
• Data Storage

Programming

• Heptavintimal
• Construct
• T Language

Implementation

• Binary-Coded Ternary

• Current Simulator Project
• Other CircuitVerse Projects

Other Implementations

• Low Open High
• NZP
• FPGA
• Custom Chip

Binary-Coded Ternary Circuits

Gates

• NEG
• ANY
• CON
• MUL
• SUM
• RDN
• RUP

Logic

• MUX
• Half Adder
• Full Adder

Operations

• Incrementer
• Adder
• Multiplier
• Shifts
• Rotate